Adiabatic quantum-flux-parametron (AQFP) logic can operate with bit energies below 50k_BT at a clock frequency of 5 GHz, which makes it a suitable foundation for building energy-efficient computing systems. Serializer/Deserializer (SerDes) circuits are important components for general digital design. For example, complex circuits such as a microprocessor would benefit from SerDes blocks to facilitate testing during experimental measurement, or to convert bitstream data into workable parallel data words that a special purpose accelerator would operate on. Previously, we developed 8-bit AQFP-based SerDes circuits and demonstrated fully correct operation up to 2.5 GHz. Because of the free-running, non-gated clock needed for AQFP, their design differs than that of their SFQ variants which have separate load and read control clocks. Instead, the AQFP variants use a debug control signal to isolate data of interest or block subsequent dataflow from interfering with the serialization/parallelization process.

In this work, we optimized the SerDes components by using a more compact variant of AQFP logic gates and rearchitecting the buffering schemes. The result is a scalable bit-sliced design, which was especially effective for the serializer block when compared to our previous work. This enabled us to implement 16-bit versions of the SerDes components using the AIST 10 kA/cm² Nb/AlO_x/Nb high-speed standard process (HSTP). Each of the 16-bit SerDes components uses approximately 800 Josephson junctions and occupy an area of about 1.5 mm² each including peripheral circuitry for testing. The chips were fabricated by AIST and we conducted low-temperature testing showing full operation. We plan to use these circuits for testing large-scale designs such as a microprocessor as well as providing an interface for bitstream data in streaming applications.

Keywords: SerDes, adiabatic, aqfp, digital circuits