Quantum computing technologies are expected to enable fast scientific computation and secure communication. The main obstacle to demonstrating such useful applications is the high error rates of qubits. To mitigate this problem, we can use quantum error correction (QEC) technologies, i.e., encoding logical qubits with several noisy physical qubits to detect and estimate occurred physical errors. In particular, surface codes are one of the most promising candidates for QEC codes since they show high error-correction performance and it is easy to implement with the nearest neighboring qubits. There are several blueprint papers for creating large-scale quantum computing implementing error-correction mechanisms. According to the recent resource estimation, around one mega qubits are required to demonstrate computation faster than the current state-of-the-art computation [1,2].
Since we employ large code distances (around 21 to 31) to achieve sufficiently small error rates, there are two differences between existing and quantum computing architecture. One is the difficulties of error estimations. It is known that the optimal error estimation of surface codes is known to be NP-hard, and even with highly approximated algorithms, it takes non-negligible time compared to the lifetime of qubits. When the throughput of error estimation is slower than the inverse of a lifetime, quantum computing systems will not work. Thus, designing error-correction digital circuits that can deal with qubits in practical parameter regimes is one of the most vital challenges in developing fault-tolerant quantum computing.
The other part is the design of fault-tolerant operations on encoded information. Since we use QEC codes with large code distances, a naive implementation of universal operations results in long latency, and an unacceptable number of errors would be accumulated during the operations. To mitigate this problem, we can achieve Clifford logical operations by changing the projected code space, such as lattice surgery, lattice rotation, and twist [3]. Non-Clifford operations can be implemented via magic-state preparation and gate teleportation, and thus we can perform universal operations fault-tolerantly. Due to this structure, the conditions to execute multiple logical operations in parallel are different from that in that without error correction. Considering and improving the instruction-level parallelism is vital for improving the computing performance of fault-tolerant quantum computing and also necessary for estimating the minimum hardware requirement to demonstrate quantum computational advantage.
In this talk, using ground-energy estimation for the condensed matter Hamiltonian as a benchmark problem, I will present resource estimation of quantum phase estimation based on quantum-circuit synthesis, place, and routing. Based on the results, we estimate the runtime and required code distances in several scenarios. I introduce several numerical techniques obtained from the analogy of existing high-performance computing and show they behave essentially similarly to our methods [2,4].
Next, we show the synthesized error-decoding circuits on FPGA satisfying the restrictions. With moderate assumptions, we can deal with qubits with practical error rates up to distances up to about 15 [5,6].
Finally, I will discuss the extension of FTQC architecture to reduce the burden of hardware implementation. We show that with negligible overhead, we can mitigate the effect of error-rate variations of physical qubits due to inhomogeneous fabrications [5] and time-varying properties of qubits due to cosmic-ray strike or qubit leakage [6] without changing the design of physical qubits. In the early regime of FTQC, code distances would not be sufficient, and we also show a method to mitigate such errors due to insufficient code distances and magic states [7].
[1] R. Babbush, et al., "Encoding Electronic Spectra in Quantum Circuits with Linear T Complexity", Physical Review X, 8(4), 041015 (2018).
[2] N. Yoshioka, et al., "Hunting for quantum-classical crossover in condensed matter problems“, preprint arXiv:2210.14109 (2022)
[3] A. G. Fowler, et al., "Low overhead quantum computation using lattice surgery", arXiv preprint arXiv:1808.06709 (2018)
[4] Y. Suzuki, et al., “Circuit Designs for Practical-Scale Fault-Tolerant Quantum Computing”, 2023 Symposium on VLSI Technology and Circuits (2023) (Invited)
[5] W. Liao, et al., “WIT-Greedy: Hardware System Design of Weighted ITerative Greedy Decoder for Surface Code”, 28th Asia and South Pacific Design Automation Conference (ASP-DAC 2023), pp. 209-215 (2023)
[6] Y. Suzuki, et al., "Q3DE: A fault-tolerant quantum computer architecture for multi-bit burst errors by cosmic rays", the 55th IEEE/ACM International Symposium on Microarchitecture (MICRO), pp. 1110-1125 (2022)
[7] Y. Suzuki, et al., “Quantum Error Mitigation as a Universal Error Reduction Technique: Applications from the NISQ to the Fault-Tolerant Quantum Computing Eras”, PRX Quantum 3, 010345 (2022)
This work is supported by MEXT Q-LEAP Grant No.JPMXS0120319794 and JPMXS0118068682, JST Moonshot R&D, Grant No.JPMJMS2061.