RSFQ circuits are expected to realize energy-efficient high-performance computing systems. RSFQ circuits use pulse logic. Namely, voltage pulses are used for calculating logic functions.

Recently, neural networks are utilized to process various intelligent tasks such as image recognition. In the processing in the inference phase of neural networks, many multiplications are performed. Thus, implementing many multipliers in a chip is desired. Because high precision is not requested in the processing, low-precision or approximate arithmetic circuits and flexible precision circuits which can change calculation precision online have been proposed for CMOS circuits.

In this paper, a flexible-precision multiplier for RSFQ circuits is proposed. It treats operands whose bit-width n is in a predefined range from n_min to n_max. The precision for each multiplication can be specified. For an n-bit multiplication, it uses 2ⁿ clock cycles. In other words, higher multiplication performance can be achieved when lower precision is used.

Parallel processing arithmetic circuits used in CMOS circuits contain many signal lines and are tough for RSFQ circuits because active devices are necessary for splitting signal lines. The multiplier utilizes the bit-level processing proposed in our previous paper. The bit-level processing converts two operands of a multiplication fed in parallel into two bit-streams. Though the multiplication is carried out with an AND gate like stochastic computing, the multiplication is not stochastic and is carried out as a truncated multiplication precisely. In the flexible-precision multiplier, the generation circuits of bit-streams are modified from the original ones to calculate a multiplication with reduced bit-width correctly and some selectors for masking bits are inserted. A flexible-precision matrix multiplication circuit based on the multiplier is also shown. Because many component circuits for multipliers in it are shared, it can be realized in a small area.

We designed the layout of the proposed multiplier for AIST ADP2 process for the evaluation purpose. It can perform 3- and 4-bit multiplication. The number of Josephson junctions (JJs) in it is 1,049. The area overhead and the overhead in the number of JJs are small compared with the original design without flexible precision capability.

Keywords: RSFQ Circuits, Digital Circuits, Multiplier, Matrix Multiplication