The adiabatic quantum-flux-parametron (AQFP) logic is one kind of superconducting logic circuit family and it is spotlighted as a technology that can potentially bring forth extremely low-energy computing. However, AQFP circuits have some issues that must be overcome to bring into practical use, and improving integration is one of them.

Conventionally, a 4-phase clocking methodology has been utilized as the power-clock (i.e. provides both the bias and the clock) for AQFP circuits. This method requires elements to transmit signal currents from one phase to the next adjacent phase. However, recent papers show that an enormous number of buffers are needed simply for data synchronization. In other words, valuable area is being used only for buffering data instead of actually performing logic. We propose an N-phase clocking method to reduce the number of buffers, namely adopting the phase number N>4. When the phase number N increase by x times, it is experimentally clear that the total number of buffers can be reduced to 1/x of the original total.

If we let N be the ''global phase'' or the number of phases that the entire circuit or system will be clocked by in a single clock cycle, and we let b be the ''base phase'' that forms the basis of N as it is fundamentally the minimum number of phases an AQFP circuit can be clocked by (typically 4), we can describe a ratio r=N/b which can be re-written to show a relationship between N and b such that N = r × b. For example, when the b = 4, valid candidates for N are 8, 12, 16,... and so on.

If signals are propagating with N>4, we have some flexibility in deciding which phase can transmit the signal and which phase can receive that signal. For example, if logic gates are driven by 8-phase clock timing (N=8) where each phase is separated by 45°, and the base phase b=4 (phase separation of 90°), we can remove needless buffers as long as the transmitting phase and receiving phase are separated by no more than 90° which is determined by the base phase. This means we can skip approximately half of the buffers in the whole circuit. This is the key point of N-phase clocking.

If we let k be the number of buffers in the circuit, and we let kretim be the number of buffers after we apply N-phase retiming, we can get the following expression after considering combinations of odd and even of n and b:

k_retim = ⌊k÷r⌋

Keywords: AQFP, retiming, logic synthesis, benchmark