Adiabatic quantum-flux-parametron (AQFP) logic is known as an energy efficient superconductor logic family. It is featured with higher speed and lower power consumption than conventional CMOS logic even after considering the cooling overhead. However, it has a problem of low integration because of its limited wiring length (~1000µm). In order to solve this problem, it is necessary to increase the level of integration by optimizing the placement and wiring steps assuming that the target fabrication process has a sufficient amount of routing layers. Currently, there is already a placement optimization tool for AQFP and its wiring method is based on the Left Edge Algorithm (LEA) because it was developed for a simple fabrication process with a single dedicated routing layer. It is possible to design AQFP logic using more advanced fabrication processes with additional wiring layers. In this case, LEA is not a proper routing algorithm for AQFP. The interconnect for AQFP is wired by sandwiching the strip-lines between the ground layers. Because of this structure, horizontal lines can be wired in parallel on the same track in two-layer channel routing. This kind of routing method is not available in CMOS channel routing. Thus, we are developing a mutilayer channel routing algorithm optimized for AQFP. In this research, we have developed a generic two-layer channel routing algorithm and have shown a reduction in the number of routing tracks when compared to LEA-based routing. Furthermore, we plan to research and evaluate whether or not it can be used in the future for more advanced fabrication processes that can support multilayer channel routing with three or more layers.

Fig. 1, Comparison of two wiring results. The number of tracks was halved by the proposed method. (a) Wiring results by LEA. The number of tracks is 6. (b) Wiring results for the proposed method. The number of tracks is 3.

Keywords: AQFP, Channel routing algorithm