Single-flux quantum circuits (SFQ circuits), which are expected to be integrated circuits of next generation, are high-speed, ultra-low-power circuits that utilize the properties of superconductivity and have been actively studied in recent years. In fabricated SFQ chips, as in CMOS chips, the functionality of the fabricated circuit should be tested to ensure that it is implemented correctly. Fault detection is the process of checking for the presence of a fault,
Fault diagnosis refers to the internal identification of the physical cause of a failure in an LSI that has been determined to be faulty.　Both are collectively referred to as "testing. This test is done by inputting a set of signals, called a test pattern, into the circuit and comparing the response to an expected value.

SFQ circuits use pulse logic, which means that they use voltage pulses to calculate logic functions. In addition, logic gate has a clock input, and the gate operates in synchronization with the clock. If a pulse arrives at the data input port within the clock cycle defined by the clock pulse input, the input logic value is 1; if not, the logic value is 0.
In SFQ circuits, the timing error of the gate input pulses due to high-speed operation cannot be ignored. Due to physical factors such as variation during manufacturing, the pulse delay time to the gate deviates from the design with high frequency, and this causes a fault in which the order of arrival changes.

Thus, in SFQ circuits, timing faults that change the function of the gate, defined as "the order of arrival of pulses to the gate being different from the design," occur.
It is necessary to generate a pattern on a new model to deal with this timing failure. Since it is difficult to make the pattern manually, automatic generation using a computer is essential. Furthermore, in the process of pattern generation, it is necessary to run a huge number of fault simulations to reproduce the timing faults that occur in the circuit therefore, optimization is required for test patter generation for large-scale circuits.

An accelerated method of timing fault simulation has been proposed for fault detection. In the fault diagnosis, triples of primary input patterns are applied,
This is more difficult than fault detection with two consecutive input patterns because the critical timing locations are identified by comparing the faults as well as the correct behavior.

In this research, we aim to reduce unnecessary computation and increase speed in the fault simulation, which accounts for a large percentage of the processing time in generating test patterns for timing faults in fault diagnosis. In the fault simulation, both the normal circuit operation and the operation of the faulty circuit are simulated. Therefore, focusing on the similarity of the behavior of both circuits, only the gates in the region that can be affected by the failure are simulated in the simulation of the faulty circuit to reduce duplicate calculations. In addition, since the gates in the SFQ circuit have clock inputs, the combinational circuit has pipeline operation. Due to this nature, there are stages in each clock cycle that are not relevant to test pattern generation. Since triples of primary input patterns transitions are input for fault diagnosis, the stages that are not related to test pattern generation are different from those for fault detection, where two pairs of inputs are used. By using the clocking method, which stage should be simulated is calculated and referenced correspondingly. In this method, the simulation of the gates belonging to these stages is omitted to improve the speed.

We evaluate the effectiveness of the proposed method by conducting speed comparison experiments using existing combinational circuit data sets and measuring the generation time of test pattern generation using the proposed method.

Acknowledgments
This work was giving me very useful advice by Dr. Naofumi Takagi, Professor at the Institute of Informatics, Kyoto University.

Keywords: RSFQ circuit, timing fault, fault diagnosis, characteristics of pipeline