Adiabatic Quantum Flux Parametron (AQFP) superconductor logic circuits rely on magnetic coupling between the gate and clock and control lines to function. Circuit design engineers start by designing a circuit netlist, selecting parameters to fit design objectives, optimizing the netlist in simulation and then progressing to integrated circuit layout.

Circuit netlists designed by hand typically consist mostly of self inductance and do not contain all the mutual inductances. Though this approach is convenient for designing circuit layouts, the lack of a complete set of mutual inductances can limit the accuracy of the designed netlist. For a circuit netlist to be an exact representation of the layout, the number of inductors should be equal to the number of fundamental cycles in the netlist graph. This fundamental inductor set represents the exact number of inductors required to extract a full inductance matrix, containing all the mutual inductances.

In this paper, we verify AQFP layouts through full-circuit inductance extraction, often done with InductEx and TetraHenry. Extracted parameters, which then include self inductance and all mutual inductances specified by the designer, are then compared to design values before adjustments to the layout is made.

We show that this method produces small but possibly significant errors due to mismatch between the design schematic and the layout.

With compact simulation model extraction, which we added to the InductEx tool chain, a much more accurate simulation model that includes all mutual inductances can be obtained to verify circuit performance after layout.

We show the improvements in model fidelity for typical AQFP cells and justify the use of compact model extraction as the final step in cell library verification.

Keywords: AQFP, compact simulation model, fundamental cycles, mutual inductance