HYPRES developed an advanced design flow and design infrastructure for superconductor integrated circuits using standard CMOS based EDA tools along with internally developed tools and has been successfully using this flow for the past several years.  The design infrastructure includes the process design kit, advanced simulation methodology, and IC verification rule decks. The superconductor hierarchical circuit analyzer developed by HYPRES serves as bedrock of our simulation methodology facilitating circuit analysis and debugging including extraction of circuit parameter margins, analysis of Monte-Carlo simulations with process corners, as well as automated timing characterization. The automated timing characterization methodology developed for RSFQ circuits facilitates extraction of timing constraints and propagation delays for each cell as a function of all the possible permutations of input and output load. Using the advanced design infrastructure, we have designed a dual RSFQ/ERSFQ cell library for the MIT-LL, SFQ5ee process. In addition to satisfying the margins criterion, the performance of each cell has been optimized for Monte-Carlo statistical variations across multiple process corners including minimizing the spread of timing distributions. Using the automated timing characterization, we have generated Liberty files for multiple process corners using the load dependent as well as standard load timing tables. We compare the timing accuracy for each methodology. Accurate timing characterization of library cells has enabled adopting the standard digital design flow using EDA tools, such as HDL simulations and static timing analysis (STA) with timing back-annotation.  The digital design flow allows for scaling circuit complexity. As an example, we have designed and simulated a 64-bit ALU with 90,256 junctions with Verilog HDL and timing back-annotation across multiple process corners using Synopsys VCS tool. To validate the timing characterization methodologies, we have evaluated their timing accuracies by comparing with full circuit simulations on representative ALU sub-blocks. The load dependent timing closely matches with the timing from Spice circuit simulations. Using this proven design flow and infrastructure as a knowledge source, we have collaborated with Synopsys to enhance their tools for a full native tool enabled design flow and infrastructure, which represents a significant expansion in design capabilities and capacity for superconducting electronics. Using the 64-Bit arithmetic logic unit and a Pseudo Random Bit Sequence (PRBS) generator as reference circuits, we demonstrate the use of Synopsys tools for superconductor IC design including spice circuit simulations, plotting waveforms, margins analysis, Monte-Carlo simulations, HDL simulations with timing back-annotation, and IC verification including design rule checker and layout-versus-schematic checker. Using the cell library and the advanced design flow, a Pseudo Random Bit Sequence (PRBS-7) generator was designed with RSFQ and ERSFQ variants and fabricated in the MIT-LL 10kA/cm2, SFQ5ee process. The RSFQ, PRBS-7 circuit works up to 64 GHz clock frequency, while the ERSFQ, PRBS-7 circuit works up to 45.72 GHz clock frequency. We have also designed an 8-bit ALU. We have fabricated test circuits with sub-blocks of the ALU and confirmed functional operation with wide margins at low speed.  In addition, the cell library has also enabled the RTL to GDS flow. Using the Synopsys Fusion compiler, we have synthesized and placed and routed a 16-bit, 51-tap, FIR filter.

Keywords: Superconductor, Arithmetic Logic Unit, Integrated Circuit Design Flow, PRBS