Rapid Single Flux Quantum (RSFQ) circuits attract attention as ultra-high-speed and low-power computing devices and use pulse logic. Namely, they express logical values with voltage pulses. In RSFQ circuits, the operation of a gate changes depending on the order of pulse arrivals for its input terminals. Each gate input can obtain a function as a storage element by tuning the order of pulse arrivals. In this presentation, we call the functionality the latching function.
Recently, a method called Stochastic Computing (SC) has been actively studied in semiconductor integrated circuits. A number in SC, i.e., a Stochastic Number (SN), is expressed by a bitstream on a single wire. Namely, it is expressed by the probability of 1 in the bitstream consisting of 1 and 0. SC can perform multiplication with an AND gate. Therefore, it uses a small number of wires and gates. Thus, we can realize compact RSFQ circuits with SC.
In this presentation, we propose compact RSFQ SC circuits for computing polynomials and propose a design method. We feed an operand of a polynomial as an SN and at least one SN of an arbitrary constant value to the circuit, and we obtain the result as an SN. As an input of the design method, we give a polynomial to compute and a set of arbitrary constant values supplied as SNs.
The method proposed in this presentation consists of three steps. We transform the polynomial given as the input to a formula used for implementing it as an SC circuit as the first step. Then, as the second step, we design an internal circuit to feed constant SNs corresponding to constants in the transformed formula. We generate those SNs from the given constant SNs, which are not necessarily the same as the constants in the formula, to reduce large circuits for generating constant SNs. In this step, we first generate a set of possible constants generated from the given constant values provided as SNs using a logic circuit of the predefined depth before designing the internal circuit. We gradually grow a set of possible constants by appending new constants obtained by feeding a pair of constants SNs to a logic gate such as AND, OR, XOR, and NOT and obtain the final set of possible constants. Then, we choose the nearest constants to the necessary constants from the generated set and design the internal circuit.
As the last step of the proposed method, we minimize DFF insertions for eliminating correlations by taking advantage of the latching function of the gate input. In an arithmetic operation with SC, a correlation between operation bits in bitstreams worsens the error. An SC circuit naively designed with the constant generation circuit designed in the previous step has re-convergent paths, and its calculation error is significant. The correlation can be reduced by inserting storage elements in a data line and shifting arrivals of bits for several time frames. We insert storage elements in the paths to prevent the increase of calculation errors due to re-convergence of the same input values．We utilize the latching function to minimize the number of DFFs. We formulate this step as integer linear programming.
We implemented the method and designed a circuit to compute a function x - x^3/6 + x^5/120, which comes from the Maclaurin series of the sine function, using a constant SN 1/2. The number of gates in the circuit designed with the proposed method was reduced compared to the circuit without utilizing the latch function of an RSFQ gate input. The circuit consists of 14 logic gates and 9 DFFs and is small.

Keywords: RSFQ circuits, Stochastic Computing