Josephson-CMOS hybrid memory is a reasonable solution of large-scale cryogenic memories for Josephson integrated circuits such as single-flux-quantum (SFQ) circuits [1][2]. We have developed and demonstrated a 64-kb Josephson-CMOS hybrid random-access memory used for SFQ general-purpose computing systems so far [3]. However, the demonstrated hybrid memory worked at just low frequencies in experiments, while the target frequency was over 1 GHz. Our next target is a demonstration of the Josephson-CMOS hybrid memory at high frequency. In this study, we report the 1 GHz readout operation of the Josephson-CMOS hybrid memory using a sequential-access read-only CMOS memory. In the previous design, the CMOS amplifier, an input interface component of the Josephson-CMOS hybrid memory, limited the maximum operating frequency of the hybrid memory. To demonstrate the high-speed readout operation of the CMOS memory and Josephson readout interface, components of the hybrid memory other than CMOS amplifier, we adopted a sequential-access read-only memory in this study. In the memory design, a shift-register address decoder is used instead of a binary address decoder so that the hybrid memory performs as a sequential-access read-only memory. As a result, the memory can fully utilize the advantages of the Josephson-CMOS hybrid memory: high-throughput readout operation thanks to the cryogenic operation of CMOS devices and high sensitivity of Josephson current sensors. Though the developed memory system can only perform sequential access, some potential applications such as a dataset memory in machine learning are expected. We designed an SFQ accumulator for the test circuit, which receives the data from the hybrid memory and conducts addition calculations. We designed and fabricated a 64-kb Josephson-CMOS hybrid memory and a SFQ accumulator using the AIST 10-kA/cm2 Nb advanced process and Rohm 180 nm CMOS process. The system can read out 32-bit data from the memory with one system clock cycle. In the experiment, we obtained the correct operation of the test system with the maximum system clock frequency of 1 GHz, corresponding to a 32 Gbps readout rate. Measurement results indicate that the maximum operating frequency was limited by large parasitic inductance and capacitance in the interconnection between SFQ and CMOS chips.

[1] U. Ghoshal et al., “Superconductor-semiconductor memories,” IEEE Trans. Appl. Supercond., vol. 3, no. 1, pp. 2315-2318, Mar. 1993.
[2] T. Van Duzer et al., “64-kb hybrid Josephson 4 Kelvin RAM with 400 ps access time and 12 mW read power,” IEEE Trans. Appl. Supercond., vol. 23, no. 3, 1700504, Jun. 2013.
[3] G. Konno et al., “Fully Functional Operation of Low-Power 64-kb Josephson-CMOS Hybrid Memories,” IEEE Trans. Appl. Supercond., vol. 27, no. 4, 1300607, Jun. 2017.

Keywords: Josephson-CMOS hybrid memory, read-only memory, sequential access, SFQ circuits