Field programmable gate array (FPGA) [1] is a programmable logic device whose function is flexibly defined after manufacturing. FPGAs are currently being used in various fields, including high-performance data processing, because they can realize logic circuits optimized for each application with low cost and short development time. One problem in CMOS-based high-performance FPGAs is their power consumption, by which the operation speed and integration density are limited.
Adiabatic quantum flux parametron (AQFP) [2] logic is promising for future energy-efficient, high-performance information processing systems. Its static power is zero because of ac flux bias, and its dynamic power is very low because of the adiabatic switching of the Josephson junctions. We are developing energy-efficient FPGA by using AQFP circuits. Our previous study demonstrated an AQFP-CMOS hybrid FPGA, which is composed of AQFP logic circuits and switches and CMOS memories [3]. One issue in the hybrid FPGA is relatively high energy consumption in the CMOS memory part.
In this study, we designed and demonstrated purely AQFP-based low-power FPGA. We adopted an AQFP buffer chain memory, which enables high-density memory of the AQFP FPGA. The developed all-AQFP FPGA comprises logic blocks, switch blocks, input/output connection blocks, and buffer chain memories. Every two-input logic function can be defined by a look-up table in the logic block. In addition, the switch block also can perform some logic functions, including Majority, AND, OR functions. We fabricated the AQFP FPGA composed of one logic block, four switch blocks, four input/output connection blocks using the AIST 10 kA/cm2 Nb high-speed standard process. The circuit area is approximately 4.0 mm2, and the total junction number is 1982. The power consumption is estimated to be 14.8 nW at 5 GHz operation. We tested the functions of the AQFP FPGA at low speed and verified the correct programable operation.
[1] U. Farooq, Z. Marrakchi, and H. Mehrez, “FPGA architectures: An overview,” in Tree-Based Heterogeneous FPGA Architectures. NewYork, NY, USA: Springer-Verlag, 2012
[2] N. Takeuchi, D. Ozawa, Y. Yamanashi and N. Yoshikawa “An adiabatic quantum flux parametron as an ultra-low-power logic device,” Supercond. Sci. Technol.,2013
[3] Y. Okuma, N. Takeuchi, Y. Yamanashi and N. Yoshikawa“Design and Implementation of a Low-Power Area-Efficient Adiabatic-Quantum-Flux-Parametron FPGA using Josephson-CMOS Hybrid Memories,” IEEE Trans. Appl. Supercond., 2019
Keywords: Superconducting circuit, AQFP, FPGA