A topological quantum computer based on Majorana bound states (MBS) has attracted great interest because of its excellent robustness properties. A lot of solid state materials platforms have been experimentally shown to host Majorana signatures. Some examples are topological semimetals in combination with superconductivity. When superconductivity is induced at the surface of a topological material using the proximity effect, a MBS can occur either at an Abrikosov vortex core or at a planar Josephson junction. Since two-dimensional surface state is realized without strong magnetic field, single flux quantum (SFQ) logic circuits as classical computing part can be placed near a topological quantum computing part.
Recently manipulation method by current pulses for MBS was proposed in the topological Josephson junction arrays. The existence and dynamic stability of 2π and 4π vortices were determined in triangular and square JJ arrays because the 2π vortices required for MBS. The resistively shunted junction (RSJ) model with a current-phase relation with mixed 2π (fractional) and 4π-periodic components. The existence criterion of 2π vortices depends strongly on the inductance parameter βL and the percentage of 4π periodic current component α. Typical values were βL=3.77 and α=0.2.
In this study, we proposed SFQ logic circuits for braiding operations for topological Josephson arrays using RSJ model with βL=2.12 and α=0. The proposed SFQ logic circuits will be extended for topological Josephson arrays with α≠0.
First of all we confirmed braiding operations in triangular and square JJ arrays. Assuming SFQ logic circuits with critical current density of 10 kA/cm2 Nb process, a double flux quantum driver gate was required to manipulate 2π vortices. Correct braiding operations were confirmed for the triangular JJ array with βL=1.09-1.82, Ic=60 μA, and the square JJ array with βL=1.82-2.48, Ic=50 μA.
Next, we examined a CNOT operation for the square JJ array with βL=2.12, Ic=50 μA.
To realize the CNOT operation, more than 100 braiding operations are needed. One braiding operation is needed two current pulses, so NDRO gates were used for main components. NDRO gate array was placed corresponding to the square JJ array, including SFQ pulse propagation path of jtl, driver, ptl, receiver and DFQ gates. We confirmed a clock frequency of 125 GHz for SFQ logic circuit, 31.25 GHz for the braiding operations and 20 MHz for the CNOT operation by simulation using wr-spice.
Detail of simulation results will be presented at the conference.
Acknowledgements
This work was supported by JSPS KAKENHI Grant Number 21K18708.
This study has been partially supported by the VLSI Design and Education Center (VDEC) at the University of Tokyo, in collaboration with Cadence Design Systems, Inc.
Keywords: Topological Quantum bit, Single Flux Quantum logic, braiding